Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicron CMOS Circuits

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented

A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management

In this paper, a lightweight autonomous reconfiguration approach is developed for Field Programmable Gate Arrays (FPGAs). Under the Multilayer Runtime Reconfiguration Architecture (MRRA) paradigm, hardware configuration information is read and operated on directly at runtime to provide low overhead dynamic reconfiguration. This enables a standardized set of Application Programming Interfaces (APIs) for uniform access to heterogeneous logic and other resources. A prototype MRRA system is developed for Xilinx Virtex II Pro family of FPGAs to exercise partial reconfiguration capability. The Virtex II Pro On-Chip PowerPC core is used to control these reconfiguration protocols implemented in user logic. These two features make an autonomous reconfiguration system possible, allowing a FPGA to efficiently reconfigure itself under the control of a microprocessor core instantiated within the FPGA fabric

A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management

In this paper, a lightweight autonomous reconfiguration approach is developed for Field Programmable Gate Arrays (FPGAs). Under the Multilayer Runtime Reconfiguration Architecture (MRRA) paradigm, hardware configuration information is read and operated on directly at runtime to provide low overhead dynamic reconfiguration. This enables a standardized set of Application Programming Interfaces (APIs) for uniform access to heterogeneous logic and other resources. A prototype MRRA system is developed for Xilinx Virtex II Pro family of FPGAs to exercise partial reconfiguration capability. The Virtex II Pro On-Chip PowerPC core is used to control these reconfiguration protocols implemented in user logic. These two features make an autonomous reconfiguration system possible, allowing a FPGA to efficiently reconfigure itself under the control of a microprocessor core instantiated within the FPGA fabric

Self-Checking Fault Detection Using Discrepancy Mirrors

A method for robust detection of faults is developed based on pairwise parallel evaluation using Discrepancy Mirror logic. Discrepancy Mirrors provide coverage for the fault detector elements within the same mechanism used for the functional logic under test. The detector logic is self-testing and propagates functional outputs with adherence to a single fault-secure property so that erroneous outputs from any single fault are not propagated. Within the detector, bitwise equality comparisons are employed directly without additional data encoding/decoding schemes to determine the validity of the output. Fault handling is performed using the underlying data throughput so that additional test vectors are not required. The circuit was implemented for a Xilinx Virtex II Pro FPGA platform and fault-secure operation was verified using ModelSim-II for exhaustive stuck-at scenarios. Results indicate fault isolation in a pool of 100,000 resources using an expected value of 17.6 to 64-1pairings when as little as one half of the inputs applied articulate the fault

Smart Priority Queue Algorithms For Self-Optimizing Event Storage

Low run-time overhead, self-adapting storage policies for priority queues called smart priority queue (SPQ) techniques are developed and evaluated. The proposed SPQ policies employ a low-complexity linear queue for near-head activities and a rapid-indexing variable bin-width calendar queue for distant events. The SPQ configuration is determined by monitoring queue access behavior using cost-scoring factors and then applying heuristics to adjust the organization of the underlying data structures. To illustrate and evaluate the method, an SPQ-based scheduler for discrete event simulation has been implemented and was used to assess the resulting efficiency, components of access time, and queue usage distributions of the existing and proposed algorithms. Results indicate that optimizing storage to the spatial distribution of queue access can decrease HOLD operation cost between 25% and 250% over existing algorithms such as calendar queues. © 2004 Elsevier B.V. All rights reserved

Cache coherence in a multiport memory environment

The effects of various cache coherence strategies are analyzed for a multiported shared memory multiprocessor. Analytical models for concurrent read exclusive write access (CREW) and concurrent read concurrent write access (CRCW) are developed including shared-not-cacheable, snooping bus, snooping bus with cache-to-cache transfers, and directory protocols. The performance of each protocol is shown as the hit rate, main memory-to-cache memory cycle time ratio, fraction of shared data, read percentage, and number of partitions are varied. Overall, results indicate that a snooping bus with cache-to-cache transfer scheme provides consistently fast access times over a wide range of execution parameters. However, nearly equivalent performance can be obtained with simpler directory based schemes. The implications of these results on increasing port complexity and memory usage are discussed

Smart priority queue algorithms for self-optimizing event storage," Simulation Modeling Practice and Theory

Low run-time overhead, self-adapting storage policies for priority queues called Smart Priority Queue (SPQ) techniques are developed and evaluated. The proposed SPQ policies employ a low-complexity linear queue for near-head activities and a rapid-indexing variable bin-width calendar queue for distant events. The SPQ configuration is determined by monitoring queue access behavior using cost-scoring factors and then applying heuristics to adjust the organization of the underlying data structures. We show that optimizing storage to the spatial distribution of queue access can decrease HOLD operation cost between 25 % and 250 % over existing algorithms such as calendar queues. An SPQ-based scheduler for discrete event simulation has been implemented and was used to evaluate the resulting efficiency, components of access time, and queue usage distributions of the existing and proposed algorithms

Wire Crossing Constrained Qca Circuit Design Using Bilayer Logic Decomposition

Quantum-dot cellular automata (QCA) seek potential benefits over CMOS devices such as low-power consumption, small dimensions, and high-speed operation. Two prominent QCA concerns of wire crossing complexity and circuit robustness are addressed by developing a three-step bilayer logic decomposition (BLD) methodology to design QCA-based logic circuits. The partitioning of QCA computing operations into logic layers realises considerable improvements in complexity, area, and modularity metrics. Moreover, since larger circuits are divided into two increasingly disjoint sub-planes, verification of the functionality of the design becomes compartmentalised. Design capability of the proposed approach is illustrated and analysed by implementing an area-efficient full comparator (FC) based on a novel logic realisation. The resulting 1-bit FC achieves 32% improvement in complexity metrics in comparison with the previous optimal QCA-based FC. The related waveforms used in verification of the BLD-generated FC which are obtained by the QCADesigner simulation tool are discussed as a motivating example of the BLD methodology